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vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 2 of 13 document revision history 1: document revision from to date description changed by checked by a 2003.12.24 first release. (based on test specification vl-ts-mdls16265d-xx rev.m 2003-06-28). sunny lee yu hao
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 3 of 13 contents page no. 1. general description 4 2. mechanical specifications 4 3. interface signals 7 4. absolute maximum ratings 8 4.1 electrical maximum ratings (ta=25
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 4 of 13 varitronix limited specification of lcd module type model no.: mdls16265d-03 1. general description x 16 characters (5 x 8 dots) x 2 lines stn positive yellow reflective lcd character module. x viewing angle: 6 o?clock direction. x driving duty: 1/16 duty, 1/5 bias. x ?samsung? ks0066up-10bcc(die form) lcd c ontroller & driver or equivalent. x ?samsung? ks0065b-pcc(die form) lcd segment driver or equivalent. 2. mechanical specifications the mechanical detail is shown in fig. 1(a) and summarized in table 1 below. table 1 parameter specifications unit outline dimensions 84.0(w) x 44.0(h) x 10.0 max.(d) mm viewing area 61.0(w) x 16.0(h) mm display format 16 characters x 2 lines - character size 2.95(w) x 5.55(h) (5 x 8 dots) mm character spacing 0.6(w) x 0.4(h) mm character pitch 3.55(w) x 5.95(h) mm dot size 0.55(w) x 0.65(h) mm dot spacing 0.05(w) x 0.05(h) mm dot pitch 0.60(w) x 0.70(h) mm weight tbd grams
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 5 of 13 figure 1(a): module specification
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 6 of 13 figure 1(b): module specification
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 7 of 13 3. interface signals table 2 pin no. symbol description 1 vss ground (0v). 2 vdd power supply for logic (+5.0v). 3 v0 power supply for lcd driver. 4 rs register select input: ?high? for data register (for read and write). ?low? for instruction register (for write), busy flag, address counter (for read). 5 r/w read/write signal: ?high? for read mode. ?low? for write mode. 6 e enable. start signal for data read /write. 7 db0 data input/output (lsb) 8 db1 data input/output 9 db2 data input/output 10 db3 data input/output 11 db4 data input/output 12 db5 data input/output 13 db6 data input/output 14 db7 data input/output (msb) k led(-) cathode of led backlight a led(+) anode of led backlight
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 8 of 13 4. absolute maximum ratings 4.1 electrical maximum ratings (ta = 25 oc) table 3 parameter symbol min. max. unit power supply voltage (logic) vdd-vss -0.3 +7.0 v power supply voltage (lcd drive) vlcd =vdd-v0 -0.3 +15.0 v input voltage vin -0.3 vdd+0.3 v note: the modules may be destroyed if they are used beyond the absolute maximum ratings. all voltage values are referenced to vss = 0v. 4.2 environmental condition table 4 operating temperature (topr) storage temperature (tstg) item min. max. min. max. remark a mbient temperature 0q c +50 q c -10 q c +60 q c dry h umidity 95% max. rh for ta d 40q c < 95% rh for ta > 40 q c no condensation v ibration (iec 68-2-6) cells must be mounted on a suitable connecto r frequency: 10 a 55 hz amplitude: 0.75 mm duration: 20 cycles in each direction. 3 directions shock (iec 68-2-27) h alf-sine pulse shape pulse duration : 11 ms peak acceleration: 981 m/s 2 = 100g number of shocks : 3 shocks in 3 mutually perpendicular axes. 3 directions
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 9 of 13 5. electrical specifications 5.1 typical electrical characteristics at ta = 25 q c, vdd = 5v r 5%, vss=0v. table 5 parameter symbol conditions min. typ. max. unit supply voltage (logic) vdd -vss 4.75 5.0 5.25 v supply voltage (lcd) vlcd =vdd ?v0 vdd = 5v, note (1) 4.3 4.6 4.9 v v ih ?h? level 2.2 - vdd v input signal voltage for e,db0-db7,r/w,rs. v il ?l? level -0.3 - 0.6 v character mode, vdd=5v, note 1 - 1.0 1.5 ma supply current (logic & lcd) idd checker board mode, vdd=5v, note 1 - 1.3 2.0 ma character mode, vdd=5v, note 1 - 0.2 0.3 ma supply current (lcd) i0 checker board mode, vdd=5v, note 1 - 0.2 0.3 ma note (1): there is tolerance in optimum lcd driving voltage during production and it will be within the specified range.
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 10 of 13 5.2 timing specifications at ta = 0 q c to +50 q c, vdd = +5v r 5%, vss = 0v. refer to fig. 2 , the bus timing diagram for write mode. table 6 parameter symbol min. max. unit e cycle time tc 500 - ns e rise/fall time t r ,t f - 20 ns e pulse width(high, low) t w 230 - ns r/w and rs setup time t su1 40 - ns r/w and rs hold time t h1 10 - ns data set-up time t su2 80 - ns data hold time t h2 10 - ns refer to fig. 3 , the bus timing diagram for read mode. table 7 parameter symbol min. max. unit e cycle time tc 500 - ns e rise/fall time t r ,t f - 20 ns e pulse width(high, low) t w 230 - ns r/w and rs setup time t su 40 - ns r/w and rs hold time t h 10 - ns data output delay time t d - 120 ns data hold time t dh 5 - ns
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 1 1 of 13 figure 2: w r ite mode t i m i ng diagram figure 3: read mode t i m i ng diagram
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 12 of 13 5.3 t i ming diagram of vdd against v0. power on sequence shall m eet the requirem e nt of figure 4, the tim ing diagram of vdd against v0. vdd 0v 0v v0 95% 50ms(typical) logic supply voltage lcd supply voltage figure 4: t i m i ng diagram of vdd against v0.
vl-fs-mdls16265d-03 rev . a (mdls16265d-l v - g) dec/2003 p age 13 of 13 6. character generator rom (ks0066u-10b) ?v aritronix lim ited reserves the right to change this specification.? f ax: (852) 2343-9555. url: http://www .varitronix.com - end -

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